Microchip Technology Incorporated
Method and system for reliable and secure memory erase

Abstract:

A memory device has a switch matrix with a power supply input, a control input and a power supply output, a random access memory with a power supply connection coupled with the power supply output of the switch matrix. The switch matrix has a capacitor being chargeable by a power supply and upon receiving a control signal through the control input, the switch matrix is designed to decouple the capacitor from the power supply and the random access memory and to couple the capacitor through the power supply output with the random access memory in reverse polarity thereby providing a negative power supply to the power supply output.