Microchip Technology Incorporated
Ratiometric gain error calibration schemes for delta-sigma ADCs with capacitive gain input stages

Abstract:

An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.