Xilinx, Inc.
Low current line termination structure

Abstract:

A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive- voltage, respectively. The circuit further includes a first diode connected transistor ("DCT") coupled to the second input interface, a first switching transistor ("ST") coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.