Xilinx, Inc.
Method for adaptively utilizing programmable logic devices

Abstract:

Examples described herein provide a method for evaluating a programmable logic device (PLD) for compatibility with user designs. The method includes using a processor-based system: obtaining an indication of one or more failure bits of configuration memory of a programmable logic device (PLD); determining whether each of the one or more failure bits corresponds to a configuration memory bit to be used by a first PLD user design; if any of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as unusable for the first PLD user design; and if none of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as usable for the first PLD user design.