Xilinx, Inc.
BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION

Abstract:

Disclosed methods and systems involve, prior to mapping logic of the module to a target integrated circuit (IC) technology, estimating total delay of a module of a circuit design and determining whether or not the module is timing critical based on the total delay of the module and a timing constraint. Also prior to mapping, the module is restructured for timing optimization in response to determining that the module is timing critical. In response to determining that the module is not timing critical, and prior to mapping, the module is restructured for area optimization. The elements of the module are then mapped to the circuit elements of the target IC technology, followed by place-and-route and generating implementation data for making an IC that implements the circuit design.