Xilinx, Inc.
Automated pipeline insertion on a bus

Abstract:

The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.