Xilinx, Inc.
Flexible address mapping for a NoC in an integrated circuit

Abstract:

Embodiments herein describe a SoC that includes a mapper that identifies a destination ID for routing a transaction through a NoC. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC to transmit and receive data using the NoC. In one embodiment, the ingress logic blocks can include the mapper that identifies a destination ID for each transaction. In one embodiment, the mapper can receive a destination ID from the hardware element that submitted the transaction to the ingress logic block. In this case, the mapper can bypass the address map by using the provided destination ID. If a destination ID is not provided, however, the mapper can use an address provided in the transaction to identify the destination ID.