Xilinx, Inc.
Low power device for high-speed time-interleaved sampling

Abstract:

Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an i.sup.th sampling layer of circuits of the N sampling layers of circuits may include: (a) X.sub.i buffers configured to receive an analog signal, X.sub.i.gtoreq.1, and, (b) Y.sub.i track-and-hold circuits, each track-and-hold circuit of the Y.sub.i track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Y.sub.i.gtoreq.1, at least one buffer of the X.sub.i buffers may include an integrating buffer, N.gtoreq.i.gtoreq.1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.