Xilinx, Inc.
Post-placement and post-routing physical synthesis for multi-die integrated circuits

Last updated:

Abstract:

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing post-routing and post-placement physical synthesis optimizations. One of the methods includes receiving a circuit design of a multi-die integrated circuit (IC) device having a first die connected with a second die, wherein the circuit design specifies a respective initial component placement of each of a plurality of components on the first die and the second die. A first driver on the first die having a plurality of loads on the second die is selected. A transmit site is selected on the first die that reduces a distance between the first driver and a load of the plurality of loads on the second die. The circuit design is modified including moving the first driver to the selected transmit site on the first die.

Status:
Grant
Type:

Utility

Filling date:

24 Sep 2018

Issue date:

17 Nov 2020