Xilinx, Inc.
Low-density parity check decoder using encoded no-operation instructions

Abstract:

Low-density parity check (LDPC) decoder circuitry is configured to decode an input codeword using a plurality of circulant matrices of a parity check matrix for an LDPC code. Multiple memory banks are configured to store elements of the input codeword. A memory circuit is configured for storage of an instruction sequence. Each instruction describes for one of the circulant matrices, a corresponding layer and column of the parity check matrix and a rotation. Each instruction includes packing factor bits having a value indicative of a number of instructions of the instruction sequence to be assembled in a bundle of instructions. A bundler circuit is configured to assemble the number of instructions from the memory circuit in a bundle. The bundler circuit specifies one or more no-operation codes (NOPs) in the bundle in response to the value of the packing factor bits and provides the bundle to the decoder circuitry.