Xilinx, Inc.
Adaptive scheduling of memory requests

Abstract:

Apparatuses and method for an integrated circuit device are described. In an apparatus thereof, there is a plurality of memory controllers coupled to a plurality of memory banks. A network of switches is coupled to the plurality of memory controllers. A plurality of data processing devices is coupled to the network of switches and is configured to generate memory requests. A network controller is coupled to the network of switches and is configured to queue the memory requests and selectively issue requests to memory from the memory requests queued responsive to corresponding response times associated with the plurality of memory banks.