Xilinx, Inc.
Method and apparatus for psuedo-random interleaved analog-to-digital converter use
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Abstract:
An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.
Status:
Grant
Type:
Utility
Filling date:
7 Jul 2020
Issue date:
9 Mar 2021