Xilinx, Inc.
Encoding and decoding information for detecting and correcting bit errors

Abstract:

An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.