Xilinx, Inc.
Mitigation for FinFET technology using deep isolation

Abstract:

FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the fin and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second isolation layer has a thickness greater than a thickness of the first isolation layer.