Xilinx, Inc.
Productivity language interface for synthesized circuits

Abstract:

A system includes a hardware offload circuit and a slave processor coupled to the hardware offload circuit. The system also includes a processor coupled to the slave processor and configured to execute productivity language instructions. The processor, in response to executing the productivity language instructions, is configured to generate commands and provide the commands to the slave processor. The slave processor, in executing the commands, is configured to monitor operation of the hardware offload circuit and control operation of the hardware offload circuit.