Xilinx, Inc.
Test network for a network on a chip and a configuration network

Abstract:

A network on a chip (NoC) testing interface (NTI) includes a plurality of switches whose ports are coupled to respective endpoints. In one embodiment, the ports and endpoints are coupled to a shared bus that starts and terminates at a root device. The endpoints are assigned unique address which the NTI uses to select one of the endpoints so that test data is forwarded to a device under test (DUT) coupled to the endpoint. In one embodiment, the endpoints include selection logic for determining whether the endpoint has been selected, and if so, forwarding test data to the DUT. For example, if the endpoint receives a data vector on the bus which has an address that matches the unique address of the endpoint, the selection logic forwards the test data contained in subsequently received data vectors to the DUT until a different address is received.