Xilinx, Inc.
Time sensitive networking control circuitry

Abstract:

A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.