Xilinx, Inc.
Single event upset (SEU) mitigation for FinFET technology using fin topology

Abstract:

Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (H.sub.TOT) and a width W. The height (H.sub.TOT) is greater than an optimal height (H.sub.OPT), wherein the height H.sub.OPT is a height that would optimize speed of a FinFET transistor having the width W.