Rambus Inc.
MEMORY INTERFACE TRAINING

Abstract:

A command/address (CA) interface of a memory controller coupled to a memory component is trained (e.g., voltages and timings are adjusted to maximize signal eye opening, sample timing margins etc.) while the CA interface is operated at highest known supported controller PHY frequency. After the CA interface has been trained at highest known supported controller PHY frequency, vendor specific information (e.g., vendor ID number, clock configuration, VDDQ configuration, etc.) is read from the memory component. If the vendor specific information indicates that the CA interface may be operated at a different (e.g., higher) frequency, the memory controller reconfigures its physical interface to operate at the indicated frequency. The memory controller then re-trains its CA interface while operating the CA interface at the indicated frequency.