Rambus Inc.
Memory component for deployment in a dynamic stripe width memory system

Abstract:

In a memory component having a page buffer with 2.sup.N independently accessible regions, N bits of a command/address value are decoded to access contents within a first one of the 2.sup.N page-buffer regions if a configuration value specifies a first addressing resolution and, if the configuration value specifies a second addressing resolution, a composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2.sup.N page-buffer regions.