Rambus Inc.
COMPUTE ACCELERATED STACKED MEMORY

Abstract:

An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.