Rambus Inc.
Buffering device with status communication method for memory controller

Abstract:

In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.