Texas Instruments Incorporated
Process controlled output driver staggering

Abstract:

An output buffer includes a first group of stagger FETs coupled in parallel between a power lead and an output signal lead and a second group of stagger FETs coupled in parallel between the output signal lead and a ground lead. Each stagger FET has a gate coupled to a respective base resistor and a respective adjustable resistor. A first group of bypass FETs and a second group of bypass FETs are each coupled across the terminals of a respective adjustable resistor and the gates of the bypass FETs are coupled to either a first process-sensing signal lead or a second process-sensing signal lead.