Texas Instruments Incorporated
Charge termination circuit

Abstract:

Aspects of the disclosure include a first sense transistor having a gate and a drain configured to couple in parallel with a high-side transistor and a source terminal coupled to a first node, and a second sense transistor having a gate and a drain configured to couple in parallel with a low-side transistor, and a source terminal coupled to a third node. The circuit further includes a first comparator circuit having a first input coupled to the first node, a second input coupled to a second node, and an output, a second comparator circuit having a first input coupled to the third node, a second input coupled to a ground node, and an output, and a logic circuit having first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and an output.