Texas Instruments Incorporated
High-side gate over-voltage stress testing

Abstract:

A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.