Texas Instruments Incorporated
ARCHITECTURE TO MITIGATE OVERSHOOT/UNDERSHOOT IN A VOLTAGE REGULATOR

Abstract:

In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.