Texas Instruments Incorporated
HEMT wafer probe current collapse screening

Abstract:

A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.