Texas Instruments Incorporated
Transient-insensitive level shifter

Abstract:

In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.