Analog Devices, Inc.
INCREASING POWER EFFICIENCY IN A DIGITAL FEEDBACK CLASS D DRIVER

Last updated:

Abstract:

Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

Status:
Application
Type:

Utility

Filling date:

23 Mar 2022

Issue date:

7 Jul 2022