Applied Materials, Inc.
SEMICONDUCTOR SUBSTRATE INCLUDING STRESS MEMORIZATION LAYER

Abstract:

Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.