Advanced Micro Devices, Inc.
Speculative exit from power down mode of a dynamic random access memory rank

Abstract:

A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.