Advanced Micro Devices, Inc.
Standard cell and power grid architectures with EUV lithography

Abstract:

A system and method for creating chip layout are described. In various embodiments, a standard cell uses unidirectional tracks for power connections and signal routing. At least two tracks of the metal one layer using a minimum width of the metal one layer are placed within a pitch of a single metal gate to provide a standard cell with a two to one "gear ratio" or greater. A power signal and a ground reference signal in the metal one layer are routed in a same metal one track to provide area for other signal routing. Multiple standard cells are placed in a multi-cell layout with routes in one or more of the metal two layer and the metal three layer using minimum lengths for power connections. The layout includes no power grid with a fixed pitch.