Amazon.com, Inc.
Timing verification of non-standard library blocks

Abstract:

To check the timing of a signal path involving an integrated circuit block from an outside vendor, a signal path including a driver circuit, an interconnect, and a receiver circuit can be identified in the integrated circuit design. A substitute integrated circuit design can be generated by replacing the driver circuit of the signal path with a primitive standard library cell, providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool, and replacing the receiver circuit with one or more capacitors. A static timing analysis tool can then be executed on the substitute integrated circuit design to determine whether a propagation delay from the driver circuit to the receiver circuit of the signal path satisfies a timing requirement of the integrated circuit design.