ANSYS, Inc.
Integrated circuit composite test generation

Abstract:

A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of M.sub.i . . . j states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering M.sup.N*j combinations. Related apparatus, systems, techniques and articles are also described.