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Interrupt-free multiple buffering methods and systems

Abstract:

Methods and systems for multiple-buffered display rendering without the use of hardware or software interrupts. In a first repeating process, a processor writes data for a frame a selected frame buffer and, upon completion of the frame, a swap buffer signal is transmitted. In response to the swap buffer signal, the GPU updates a memory register of the display controller to indicate that the selected frame buffer can be used in the next display synchronization interval. In a separate repeating process, the display controller monitors memory register and, in a display synchronization interval, identifies the frame buffer to use for display.