Alibaba Group Holding Limited
COMPRESSION AND DECOMPRESSION MODULE IN A CACHE CONTROLLER FOR REDUCING OFF-CHIP DATA TRAFFIC

Abstract:

A method for performing data compression in a multi-core processor comprises retrieving a chunk of data from a data array of a cache slice, wherein the cache slice is comprised within a cache associated with the multi-core processor, wherein the cache is distributed between a plurality of cache slices, and wherein each core of the multi-core processor can access each of the plurality of cache slices. The method further comprises calculating a bit mask for the chunk of data and, using the bit mask, shifting out elements in the chunk of data corresponding to zero values, wherein zero value elements in the chunk of data are shifted out and non-zero value elements in the chunk of data are retained. Finally, the method comprises writing the bit mask and the non-zero value elements to a memory.