Alibaba Group Holding Limited
DATA CONSISTENCY TECHNIQUES FOR PROCESSOR CORE, PROCESSOR, APPARATUS AND METHOD

Abstract:

A processor core, a processor, an apparatus, and a method are disclosed. The processor core is coupled to a translation lookaside buffer and a first memory. The processor core further includes a memory processing module that includes: an instruction processing unit, adapted to identify a virtual memory operation instruction and send the virtual memory operation instruction to a bus request transceiver module; the bus request transceiver module, adapted to send the virtual memory operation instruction to an external interconnection unit; a forwarding request transceiver unit, adapted to receive the virtual memory operation instruction broadcast by the interconnection unit and send the virtual memory operation instruction to the virtual memory operation unit; and the virtual memory operation unit, adapted to perform a virtual memory operation according to the virtual memory operation instruction. An initiation core sends the virtual memory operation instruction to the interconnection unit. The interconnection unit determines, based on an operation address, to broadcast the virtual memory operation instruction to at least one of a plurality of processor cores, so that all the cores can process the virtual memory operation instruction using the same hardware logic, thereby reducing hardware logic of the processor core.