Alibaba Group Holding Limited
ACCELERATION UNIT, SYSTEM-ON-CHIP, SERVER, DATA CENTER, AND RELATED METHOD

Abstract:

An acceleration unit including a primary core and a secondary core. The primary core includes: a first on-chip memory; a primary core sequencer adapted to decode a received first cross-core copy instruction; and a primary core memory copy engine adapted to acquire a first operand from a first address in the first on-chip memory and copy the acquired first operand to a second address in a second on-chip memory of the secondary core. The secondary core includes: a second on-chip memory; a secondary core sequencer adapted to decode a received second cross-core copy instruction; and a secondary core memory copy engine adapted to acquire the first operand from the second address in the second on-chip memory and copy the acquired first operand back to the first address in the first on-chip memory.