Cadence Design Systems, Inc.
Method and system for sequential equivalence checking

Abstract:

A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable combinational logic for the gated clock, as a disjunction of the enable combinational logic of the gated clock and an enable combinational logic for each FF of a plurality of FFs that are toggled by the gated clock. The method also includes performing SEC on the two representations design, using the modified enable combinational logic for the gated clock instead of the enable combinational logic of the gated clock.