Cadence Design Systems, Inc.
Differential clock generator circuit

Abstract:

A circuit can include a non-inverter circuit configured to generate a first clock signal with a first logic state during a first period of time in response to an input clock signal having the first logic state, and with a second logic state during a second period of time in response to the input clock signal having the second logic state. The circuit can include an inverter circuit that can be configured to generate a second clock signal with the second logic state during the first period of time in response to the input clock signal having the first logic state, and with the second logic state during the second period of time in response to the input clock signal having the second logic state.