Cadence Design Systems, Inc.
System, method, and computer program product for mixed signal verification

Abstract:

The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function ("SV-UDR") associated with the electronic circuit design.