Cadence Design Systems, Inc.
Input-directed constrained random simulation

Abstract:

A system and method for input-directed constrained random simulation includes obtaining an initial state for a finite state machine (FSM) that models an electronic circuit design under test (DUT), the initial state assigning values to registers of the device under test, by providing an initial state function I(s) relating to the FSM to a satisfiability problem (SAT) solver to obtain register values that satisfy the initial state function. A random Boolean circuit R(i) is constructed. A SAT solver is queried for a satisfying assignment for a conjoined expression providing the conjunction of at least a valid-transition Boolean circuit T(s, i, s') and the random Boolean circuit R(i), the valid-transition Boolean circuit describing valid transitions of the FSM as a function of current state s, inputs i, and next state s'. The satisfying assignment is added to the end of a constructed trace.