Cadence Design Systems, Inc.
Polar decoder processor

Abstract:

In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar decoder can be configured to employ a list-to-buffer mapping state register for the even bit buffer for loading even bit values from the even bit buffer and loading odd bit values from the odd bit buffer, and updating even or odd bit values for each path at the given stage of the decoding graph.