Cadence Design Systems, Inc.
Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits

Abstract:

The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the merged set of constraints. The STA also includes determining a soft breaking point for the loop in the MMMC view for timing propagation and settling. The STA maintains consistency of breaking points across SMSC and MMMC views.