Cadence Design Systems, Inc.
Analyzing clock jitter using delay calculation engine

Abstract:

The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons--one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.