Cadence Design Systems, Inc.
Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering

Abstract:

Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.