Cadence Design Systems, Inc.
Compacting test patterns for IJTAG test

Abstract:

Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.