Cadence Design Systems, Inc.
System, method, and computer program product for displaying debugging during a formal verification

Abstract:

The present disclosure relates to a method for electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of a cover trace or an assertion counter-example associated with an electronic design. Embodiments may also include allowing, at the graphical user interface, a user to analyze the cover trace or the assertion counter-example during a debugging session. Embodiments may further include identifying a dead-end state during the analysis and converting one or more constraints used in the debugging session to soft constraints. Embodiments may further include identifying at least one trace, based upon, at least in part, the soft constraints and displaying at least one unsatisfied constraint associated with the identified trace at the graphical user interface.