Cadence Design Systems, Inc.
Systems and methods for arc-based debugging in an electronic design

Abstract:

The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design at a debugging platform without performing a model extraction phase and mapping one or more extracted timing models ("ETM") to one or more netlist objects associated with the electronic design. Embodiments may further include receiving, at the debugging platform, at least one timing arc specified by a source pin and a sink pin, wherein the at least one timing arc is associated with the electronic design. Embodiments may also include generating a worst timing path based upon, at least in part, the received at least one timing arc. Embodiments may further include generating characterization information for the at least one timing arc based upon, at least in part, one or more user-specified boundary conditions.