Cadence Design Systems, Inc.
Method and system for profiling performance of a system on chip

Abstract:

A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.